// The most import things here is to make sure the Control Flow of Both ISQ and IBUF

module frv_idu_top 
import frv_types::*;
(
    input                       clk             ,
    input                       rst_n           ,
    // Program Downloader Interface
    input                       pd_rst          ,
    // Flush Interface
    input                       exp_flush       , // Exception Flush
    input                       bru_flush       , // Branch Prediction failed Flush
    input                       ret_flush_stall ,
    // Retire Interface
    input                       ret_rd_req      ,
    input [5:0]     ret_inst_id     , // ROB Read Pointer Val 
    input                       ret_flush_rles  , 
    //Foward Interface
    input                       lsu_fwd_vld     ,
    input                       lsu_fwd_rd_vld  ,
    input [5:0]     lsu_fwd_inst_id ,
    input                       bru_fwd_vld     ,
    input                       bru_fwd_rd_vld  ,
    input [5:0]     bru_fwd_inst_id ,
    input                       alu_fwd_vld     ,
    input                       alu_fwd_rd_vld  ,
    input [5:0]     alu_fwd_inst_id ,
    // =============================
    // Inst Queue Interface
    output                      ib_rreq         , // Inst queue request
    input                       ib_inst_vld     , 
    input [31:0]                ib_inst_data    ,
    input [31:0]                ib_pc_data      ,
    input                       ib_exp_vld      ,
    input [4:0]                 ib_exp_code     ,
    input [31:0]                ib_bp_taddr     , // bp target addr
    input                       ib_bp_taken     , 
    input [3:0]                 ib_bp_bhtv      , // BHT Entry Value
    input [31:0]                ib_bp_phtv      , // PHT Entry Value
    // =============================
    // Issue Queue Interface
    input                       isu_ready       , // Issue Queue Ready , when issue queue is full , isu_ready will be pull up
    output                      isq_wreq        , // Issue Queue Write Request,The Inst Entry must be valid before push into ISQ
    output [31:0]               isq_inst_data   , 
    output [5:0]    isq_inst_id     , 
    output                      isq_exp_vld     , 
    output [4:0]                isq_exp_code    ,  
    output [31:0]               isq_pc_data     , 
    //ALU Control Interface
    output                      isq_alu_vld     , 
    output                      isq_alu_land    , 
    output                      isq_alu_lor     , 
    output                      isq_alu_lxor    , 
    output                      isq_alu_sll     , 
    output                      isq_alu_srl     ,
    output                      isq_alu_sra     ,
    output                      isq_alu_add     ,
    output                      isq_alu_sub     ,
    output                      isq_alu_slt     ,
    output                      isq_alu_unsign  ,
    //Branch Control Interface
    output                      isq_bru_vld     ,
    output                      isq_bru_beq     ,
    output                      isq_bru_bne     ,
    output                      isq_bru_blt     ,
    output                      isq_bru_bge     ,
    output                      isq_bru_jal     ,
    output                      isq_bru_jalr    ,
    output [31:0]               isq_bp_taddr    , // bp target addr
    output                      isq_bp_taken    , // bp taken
    output [3:0]                isq_bp_bhtv     , // BHT Entry Value
    output [31:0]               isq_bp_phtv     , // PHT Entry Value
    //LSU Control Interface
    output                      isq_lsu_vld     ,
    output                      isq_lsu_unsign  ,
    output                      isq_lsu_load    ,
    output                      isq_lsu_store   ,
    output                      isq_lsu_word    ,
    output                      isq_lsu_half    ,
    output                      isq_lsu_byte    ,
    //MDU Control Interface
    //TODO
    //CSR Control Interface
    output                      isq_csr_vld     ,
    output                      isq_csr_write   ,
    output                      isq_csr_set     ,
    output                      isq_csr_clr     , // CSR Clear
    //Operation number Interface
    output                      isq_rs1_vld     ,
    output[5:0]     isq_rs1_ind     ,
    output                      isq_rs1_type    ,
    output                      isq_rs1_ready   ,
    output                      isq_rs2_vld     ,
    output[5:0]     isq_rs2_ind     ,
    output                      isq_rs2_type    ,
    output                      isq_rs2_ready   ,
    output                      isq_imm_vld     ,
    output [31:0]               isq_imm_data    , // here we can compress the width
    output                      isq_rd_vld      ,
    output [4:0]                isq_rd_ind      ,
    // output [5:0]    isq_rdm_ind     ,
    output                      isq_pc_used      // jal and auipc will use the pc value    
);

dec_pkt_t dec_op;

wire [31:0] dec_inst_data;
 
wire [4:0]                rat_rs1_ind        ; 
wire [4:0]                rat_rs2_ind        ; 
wire                      rat_req            ;
wire                      rat_rd_vld         ; 
wire [4:0]                rat_rd_ind         ; 
// wire [5:0]    rat_rob_wprt       ; 
// Reg Map Result
wire[5:0]     rat_rs1_map        ;
wire                      rat_rs1_type       ; // ARCH: 0 ,ROB: 1
wire                      rat_rs1_ready      ;
wire[5:0]     rat_rs2_map        ;
wire                      rat_rs2_type       ; // ARCH: 0 ,ROB: 1
wire                      rat_rs2_ready      ;
// ISQ output 
// =============================
// Issue Queue Interface
wire                      isq_wreq_nxt        ; // Issue Queue Write Request,The Inst Entry must be valid before push into ISQ
wire [31:0]               isq_inst_data_nxt   ; 
wire                      isq_exp_vld_nxt     ; 
wire [4:0]                isq_exp_code_nxt    ;  
wire [31:0]               isq_pc_data_nxt     ; 
    //ALU Control Interface
wire                      isq_alu_vld_nxt     ; 
wire                      isq_alu_land_nxt    ; 
wire                      isq_alu_lor_nxt     ; 
wire                      isq_alu_lxor_nxt    ; 
wire                      isq_alu_sll_nxt     ; 
wire                      isq_alu_srl_nxt     ;
wire                      isq_alu_sra_nxt     ;
wire                      isq_alu_add_nxt     ;
wire                      isq_alu_sub_nxt     ;
wire                      isq_alu_slt_nxt     ;
wire                      isq_alu_unsign_nxt  ; 
    //Branch Control Interface
wire                      isq_bru_vld_nxt     ;
wire                      isq_bru_beq_nxt     ;
wire                      isq_bru_bne_nxt     ;
wire                      isq_bru_blt_nxt     ;
wire                      isq_bru_bge_nxt     ;
wire                      isq_bru_jal_nxt     ;
wire                      isq_bru_jalr_nxt    ;
wire [31:0]               isq_bp_taddr_nxt    ; // bp target addr
wire                      isq_bp_taken_nxt    ; // bp taken
wire [3:0]                isq_bp_bhtv_nxt     ; // BHT Entry Value
wire [31:0]               isq_bp_phtv_nxt     ; // PHT Entry Value
    //LSU Control Interface
wire                      isq_lsu_vld_nxt     ;
wire                      isq_lsu_unsign_nxt  ;
wire                      isq_lsu_load_nxt    ;
wire                      isq_lsu_store_nxt   ;
wire                      isq_lsu_word_nxt    ;
wire                      isq_lsu_half_nxt    ;
wire                      isq_lsu_byte_nxt    ;
//MDU Control Interface
//TODO
//CSR Control Interface
wire                      isq_csr_vld_nxt     ;
wire                      isq_csr_write_nxt   ;
wire                      isq_csr_set_nxt     ;
wire                      isq_csr_clr_nxt     ; // CSR Clear
//Operation number Interface
wire                      isq_rs1_vld_nxt     ;
wire                      isq_rs2_vld_nxt     ;
wire                      isq_imm_vld_nxt     ;
wire [31:0]               isq_imm_data_nxt    ; // here we can compress the width
wire                      isq_rd_vld_nxt      ;
wire [4:0]                isq_rd_ind_nxt      ;
// wire [5:0]    isq_rdm_ind_nxt     ;
wire                      isq_pc_used_nxt     ;// jal and auipc will use the pc value    

wire                      isq_write_vld       ;

//Inst ID Gen
wire[5:0]   inst_id_gen,inst_id_gen_nxt;
wire[5:0]   isq_inst_id_nxt;


assign dec_inst_data = ib_inst_data;

assign isq_write_vld      = ib_inst_vld && isu_ready && ~bru_flush;

assign isq_wreq_nxt       = isq_write_vld;

assign isq_inst_data_nxt  = dec_inst_data; 
assign isq_exp_vld_nxt    = ib_exp_vld;
assign isq_exp_code_nxt   = ib_exp_code;
assign isq_pc_data_nxt    = ib_pc_data;

//ALU Control Interface
assign isq_alu_vld_nxt    = dec_op.pm_alu && dec_op.legal;
assign isq_alu_land_nxt   = dec_op.land;
assign isq_alu_lor_nxt    = dec_op.lor; 
assign isq_alu_lxor_nxt   = dec_op.lxor; 
assign isq_alu_sll_nxt    = dec_op.sll; 
assign isq_alu_srl_nxt    = dec_op.srl; 
assign isq_alu_sra_nxt    = dec_op.sra; 
assign isq_alu_add_nxt    = dec_op.add; 
assign isq_alu_sub_nxt    = dec_op.sub; 
assign isq_alu_slt_nxt    = dec_op.slt; 
assign isq_alu_unsign_nxt = dec_op.unsign; 

//BRU Control Interface
assign isq_bru_vld_nxt    = (dec_op.condbr || dec_op.jal) && dec_op.legal;
assign isq_bru_beq_nxt    = dec_op.beq;
assign isq_bru_bne_nxt    = dec_op.bne;
assign isq_bru_blt_nxt    = dec_op.blt;
assign isq_bru_bge_nxt    = dec_op.bge;
assign isq_bru_jal_nxt    = dec_op.jal && dec_op.pc;
assign isq_bru_jalr_nxt   = dec_op.jal && dec_op.imm12;
assign isq_bp_taddr_nxt   = ib_bp_taddr; // bp target addr
assign isq_bp_taken_nxt   = ib_bp_taken; // bp taken
assign isq_bp_bhtv_nxt    = ib_bp_bhtv ; // BHT Entry Value
assign isq_bp_phtv_nxt    = ib_bp_phtv ; // PHT Entry Value

//LSU Control Interface
assign isq_lsu_vld_nxt    = dec_op.lsu && dec_op.legal;  
assign isq_lsu_unsign_nxt = dec_op.unsign;  
assign isq_lsu_load_nxt   = dec_op.load;  
assign isq_lsu_store_nxt  = dec_op.store;  
assign isq_lsu_word_nxt   = dec_op.word;  
assign isq_lsu_half_nxt   = dec_op.half;  
assign isq_lsu_byte_nxt   = dec_op.by;  

//CSR Control Interface
assign isq_csr_vld_nxt    = dec_op.csr_read || dec_op.csr_write;  
assign isq_csr_write_nxt  = dec_op.csr_write;  
assign isq_csr_set_nxt    = dec_op.csr_set;  
assign isq_csr_clr_nxt    = dec_op.csr_clr;  

//Operation Nums

assign isq_rs1_vld_nxt    = dec_op.rs1; 
assign isq_rs2_vld_nxt    = dec_op.rs2; 
assign isq_imm_vld_nxt    = dec_op.imm12 | dec_op.csr_imm | dec_op.shimm5 | dec_op.imm20 | dec_op.load;
assign isq_imm_data_nxt   = (dec_op.imm12 | dec_op.load ? { {20{dec_inst_data[31]}} , dec_inst_data[31:20] } : 32'b0) | 
                            (dec_op.csr_imm ? {  27'b0 , dec_inst_data[19:15] } : 32'b0) |
                            (dec_op.shimm5  ? { {27{dec_inst_data[24]}} , dec_inst_data[24:20] } : 32'b0) |
                            (dec_op.store	  ?	{ {20{dec_inst_data[31]}} , dec_inst_data[31:25] , dec_inst_data[11:7] } : 32'b0) |
                            (dec_op.imm20	&& dec_op.jal  ?	{ {12{dec_inst_data[31]}} , dec_inst_data[19:12] , dec_inst_data[20] , dec_inst_data[30:21] , 1'b0 } : 32'b0) | 
                            (dec_op.condbr  ?	{ {20{dec_inst_data[31]}} , dec_inst_data[7] , dec_inst_data[30:25]  , dec_inst_data[11:8]  , 1'b0 } : 32'b0) |
                            (dec_op.imm20 && dec_op.pm_alu ? { dec_inst_data[31:12] , 12'b0}: 32'b0); 
assign isq_rd_vld_nxt     = dec_op.rd; 
assign isq_rd_ind_nxt     = dec_inst_data[11:7];

// assign isq_rdm_ind_nxt    = rob_winst_id; 

assign isq_pc_used_nxt    = dec_op.pc; 

//RAT Conncetion
assign rat_rs1_ind  =  dec_inst_data[19:15];
assign rat_rs2_ind  =  dec_inst_data[24:20];
//the rd vld can only be updated when the Inst is valid and the ISQ can recieve Instruction
assign rat_rd_vld   =  ib_inst_vld && dec_op.rd && isu_ready;

assign rat_rd_ind   =  dec_inst_data[11:7];
// assign rat_rob_wprt =  rob_winst_id;

assign isq_rs1_ind    = rat_rs1_map; 
assign isq_rs2_ind    = rat_rs2_map; 
assign isq_rs1_type   = rat_rs1_type; 
assign isq_rs2_type   = rat_rs2_type; 
assign isq_rs1_ready  = rat_rs1_ready;
assign isq_rs2_ready  = rat_rs2_ready;

//Inst Generator
assign inst_id_gen_nxt = bru_flush ? (bru_fwd_inst_id+1) :
                         isq_write_vld ? inst_id_gen + 1 :
                         inst_id_gen;

assign isq_inst_id_nxt = inst_id_gen;

wire isq_entry_wen;


frv_idu_dec _dec_dec_ctl(dec_inst_data,dec_op);

frv_idu_rat _frv_idu_rat(
.clk                    (clk            ), 
.rst_n                  (rst_n          ), 
.pd_rst                 (pd_rst         ), 
.rat_rs1_ind            (rat_rs1_ind    ), 
.rat_rs2_ind            (rat_rs2_ind    ), 
// .rat_req                (rat_req        ),
.isq_entry_wen          (isq_entry_wen  ),
.rat_rd_vld             (rat_rd_vld     ), 
.rat_rd_ind             (rat_rd_ind     ), 
.rat_rob_wprt           (inst_id_gen    ), 
.ret_rd_req             (ret_rd_req     ),
// .ret_rd_ind             (ret_rd_ind     ),
.ret_inst_id            (ret_inst_id    ), // ROB Read Pointer Val 
.ret_flush_rles         (ret_flush_rles      ), 
.lsu_fwd_vld            (lsu_fwd_vld    ),
.lsu_fwd_rd_vld         (lsu_fwd_rd_vld ),
.lsu_fwd_inst_id        (lsu_fwd_inst_id),
.bru_fwd_vld            (bru_fwd_vld    ),
.bru_fwd_rd_vld         (bru_fwd_rd_vld ),
.bru_fwd_inst_id        (bru_fwd_inst_id),
.alu_fwd_vld            (alu_fwd_vld    ),
.alu_fwd_rd_vld         (alu_fwd_rd_vld ),
.alu_fwd_inst_id        (alu_fwd_inst_id),
.rat_rs1_map            (rat_rs1_map    ),
.rat_rs1_type           (rat_rs1_type   ), // ARCH: 0 ,ROB: 1
.rat_rs1_ready          (rat_rs1_ready  ),
.rat_rs2_map            (rat_rs2_map    ),
.rat_rs2_type           (rat_rs2_type   ), // ARCH: 0 ,ROB: 1
.rat_rs2_ready          (rat_rs2_ready  )    
);
// Dffs

wire isq_write_en;

assign isq_entry_wen = ib_rreq && ib_inst_vld ;

assign ib_rreq = isu_ready;
// dffr #(1) ib_rreq_ff(clk,rst_n,1'b1,isu_ready,ib_rreq);
dffr #(.DW(5+1))        inst_id_gen_ff   (clk,rst_n,1'b1,inst_id_gen_nxt  ,inst_id_gen   );
//

wire ret_flush_rles_delay;

dffr #(.DW(1 ))  ret_flush_rles_ff      (clk,rst_n,1'b1,ret_flush_rles,ret_flush_rles_delay      ); // Issue Queue Write Request,The Inst Entry must be valid before push into ISQ


assign isq_wreq = isq_write_en && ~bru_flush && isu_ready && ~ret_flush_rles_delay;

// assign isq_wreq_wen = ib_inst_vld;

// dffr #(.DW(1 ))                      isq_wreq_ff      (clk,rst_n,isq_wreq_wen,isq_wreq_nxt     ,isq_write_en      ); // Issue Queue Write Request,The Inst Entry must be valid before push into ISQ
dffr #(.DW(1 ))                      isq_wreq_ff      (clk,rst_n,isq_entry_wen,isq_wreq_nxt     ,isq_write_en      ); // Issue Queue Write Request,The Inst Entry must be valid before push into ISQ

dffr #(.DW(32))                     isq_inst_data_ff (clk,rst_n,isq_entry_wen,isq_inst_data_nxt,isq_inst_data ); 
dffr #(.DW(5+1))        isq_inst_id_ff   (clk,rst_n,isq_entry_wen,isq_inst_id_nxt  ,isq_inst_id   );
dffr #(.DW(1))                      isq_exp_vld_ff   (clk,rst_n,isq_entry_wen,isq_exp_vld_nxt  ,isq_exp_vld   ); 
dffr #(.DW(5))                      isq_exp_code_ff  (clk,rst_n,isq_entry_wen,isq_exp_code_nxt ,isq_exp_code  );  
dffr #(.DW(32))                     isq_pc_data_ff   (clk,rst_n,isq_entry_wen,isq_pc_data_nxt  ,isq_pc_data   ); 
//ALU Control Interface
dffr #(.DW(1))                      isq_alu_vld_ff   (clk,rst_n,isq_entry_wen,isq_alu_vld_nxt   ,isq_alu_vld   ); 
dffr #(.DW(1))                      isq_alu_land_ff  (clk,rst_n,isq_entry_wen,isq_alu_land_nxt  ,isq_alu_land  ); 
dffr #(.DW(1))                      isq_alu_lor_ff   (clk,rst_n,isq_entry_wen,isq_alu_lor_nxt   ,isq_alu_lor   ); 
dffr #(.DW(1))                      isq_alu_lxor_ff  (clk,rst_n,isq_entry_wen,isq_alu_lxor_nxt  ,isq_alu_lxor  ); 
dffr #(.DW(1))                      isq_alu_sll_ff   (clk,rst_n,isq_entry_wen,isq_alu_sll_nxt   ,isq_alu_sll   ); 
dffr #(.DW(1))                      isq_alu_srl_ff   (clk,rst_n,isq_entry_wen,isq_alu_srl_nxt   ,isq_alu_srl   );
dffr #(.DW(1))                      isq_alu_sra_ff   (clk,rst_n,isq_entry_wen,isq_alu_sra_nxt   ,isq_alu_sra   );
dffr #(.DW(1))                      isq_alu_add_ff   (clk,rst_n,isq_entry_wen,isq_alu_add_nxt   ,isq_alu_add   );
dffr #(.DW(1))                      isq_alu_sub_ff   (clk,rst_n,isq_entry_wen,isq_alu_sub_nxt   ,isq_alu_sub   );
dffr #(.DW(1))                      isq_alu_slt_ff   (clk,rst_n,isq_entry_wen,isq_alu_slt_nxt   ,isq_alu_slt   );
dffr #(.DW(1))                      isq_alu_unsign_ff(clk,rst_n,isq_entry_wen,isq_alu_unsign_nxt,isq_alu_unsign);
//Branch Control Interface
dffr #(.DW(1) )                     isq_bru_vld_ff  (clk,rst_n,isq_entry_wen,isq_bru_vld_nxt   ,isq_bru_vld );
dffr #(.DW(1) )                     isq_bru_beq_ff  (clk,rst_n,isq_entry_wen,isq_bru_beq_nxt   ,isq_bru_beq );
dffr #(.DW(1) )                     isq_bru_bne_ff  (clk,rst_n,isq_entry_wen,isq_bru_bne_nxt   ,isq_bru_bne );
dffr #(.DW(1) )                     isq_bru_blt_ff  (clk,rst_n,isq_entry_wen,isq_bru_blt_nxt   ,isq_bru_blt );
dffr #(.DW(1) )                     isq_bru_bge_ff  (clk,rst_n,isq_entry_wen,isq_bru_bge_nxt   ,isq_bru_bge );
dffr #(.DW(1) )                     isq_bru_jal_ff  (clk,rst_n,isq_entry_wen,isq_bru_jal_nxt   ,isq_bru_jal );
dffr #(.DW(1) )                     isq_bru_jalr_ff (clk,rst_n,isq_entry_wen,isq_bru_jalr_nxt  ,isq_bru_jalr);
dffr #(.DW(32))                     isq_bp_taddr_ff (clk,rst_n,isq_entry_wen,isq_bp_taddr_nxt  ,isq_bp_taddr); // bp target addr
dffr #(.DW(1) )                     isq_bp_taken_ff (clk,rst_n,isq_entry_wen,isq_bp_taken_nxt  ,isq_bp_taken); // bp taken
dffr #(.DW(4) )                     isq_bp_bhtv_ff  (clk,rst_n,isq_entry_wen,isq_bp_bhtv_nxt   ,isq_bp_bhtv ); // BHT Entry Value
dffr #(.DW(32))                     isq_bp_phtv_ff  (clk,rst_n,isq_entry_wen,isq_bp_phtv_nxt   ,isq_bp_phtv ); // PHT Entry Value
//LSU Control Interface
dffr #(.DW(1))                      isq_lsu_vld_ff     (clk,rst_n,isq_entry_wen,isq_lsu_vld_nxt   ,isq_lsu_vld   );
dffr #(.DW(1))                      isq_lsu_unsign_ff  (clk,rst_n,isq_entry_wen,isq_lsu_unsign_nxt,isq_lsu_unsign);
dffr #(.DW(1))                      isq_lsu_load_ff    (clk,rst_n,isq_entry_wen,isq_lsu_load_nxt  ,isq_lsu_load  );
dffr #(.DW(1))                      isq_lsu_store_ff   (clk,rst_n,isq_entry_wen,isq_lsu_store_nxt ,isq_lsu_store );
dffr #(.DW(1))                      isq_lsu_word_ff    (clk,rst_n,isq_entry_wen,isq_lsu_word_nxt  ,isq_lsu_word  );
dffr #(.DW(1))                      isq_lsu_half_ff    (clk,rst_n,isq_entry_wen,isq_lsu_half_nxt  ,isq_lsu_half  );
dffr #(.DW(1))                      isq_lsu_byte_ff    (clk,rst_n,isq_entry_wen,isq_lsu_byte_nxt  ,isq_lsu_byte  );
//MDU Control Interface
//TODO
//CSR Control Interface
dffr #(.DW(1))                      isq_csr_vld_ff     (clk,rst_n,isq_entry_wen,isq_csr_vld_nxt  ,isq_csr_vld  );
dffr #(.DW(1))                      isq_csr_write_ff   (clk,rst_n,isq_entry_wen,isq_csr_write_nxt,isq_csr_write);
dffr #(.DW(1))                      isq_csr_set_ff     (clk,rst_n,isq_entry_wen,isq_csr_set_nxt  ,isq_csr_set  );
dffr #(.DW(1))                      isq_csr_clr_ff     (clk,rst_n,isq_entry_wen,isq_csr_clr_nxt  ,isq_csr_clr  ); // CSR Clear
//Operation number Interface
dffr #(.DW(1)              )        isq_rs1_vld_ff  (clk,rst_n,isq_entry_wen,isq_rs1_vld_nxt  ,isq_rs1_vld  );
// dffr #(.DW(5+1))        isq_rs1_ind_ff  (clk,rst_n,isq_entry_wen,isq_rs1_ind_nxt  ,isq_rs1_ind  );
dffr #(.DW(1)              )        isq_rs2_vld_ff  (clk,rst_n,isq_entry_wen,isq_rs2_vld_nxt  ,isq_rs2_vld  );
// dffr #(.DW(5+1))        isq_rs2_ind_ff  (clk,rst_n,isq_entry_wen,isq_rs2_ind_nxt  ,isq_rs2_ind  );
// dffr #(.DW(5+1))        isq_rdm_ind_ff  (clk,rst_n,isq_entry_wen,isq_rdm_ind_nxt  ,isq_rdm_ind  );
dffr #(.DW(1)              )        isq_pc_used_ff  (clk,rst_n,isq_entry_wen,isq_pc_used_nxt  ,isq_pc_used  ); // jal and auipc will use the pc value    
dffr #(.DW(1)              )        isq_imm_vld_ff  (clk,rst_n,isq_entry_wen,isq_imm_vld_nxt  ,isq_imm_vld  );
dffr #(.DW(5)              )        isq_rd_ind_ff   (clk,rst_n,isq_entry_wen,isq_rd_ind_nxt   ,isq_rd_ind   );
dffr #(.DW(1)              )        isq_rd_vld_ff   (clk,rst_n,isq_entry_wen,isq_rd_vld_nxt   ,isq_rd_vld   );
// dffr #(.DW(1)              )        isq_rs2_type_ff (clk,rst_n,isq_entry_wen,isq_rs2_type_nxt ,isq_rs2_type );
// dffr #(.DW(1)              )        isq_rs1_type_ff (clk,rst_n,isq_entry_wen,isq_rs1_type_nxt ,isq_rs1_type );
dffr #(.DW(32)             )        isq_imm_data_ff (clk,rst_n,isq_entry_wen,isq_imm_data_nxt ,isq_imm_data ); // here we can compress the width
// dffr #(.DW(1)              )        isq_rs1_ready_ff(clk,rst_n,isq_entry_wen,isq_rs1_ready_nxt,isq_rs1_ready);
// dffr #(.DW(1)              )        isq_rs2_ready_ff(clk,rst_n,isq_entry_wen,isq_rs2_ready_nxt,isq_rs2_ready);


endmodule


